--- cef_binary_3.3359.1774.gd49d25f_windows32/include/internal/cef_string_wrappers.h.orig 2019-03-09 15:59:59.571378000 +0100 +++ cef_binary_3.3359.1774.gd49d25f_windows32/include/internal/cef_string_wrappers.h 2019-03-09 16:00:08.284090000 +0100 @@ -33,6 +33,7 @@ #include #include +#include #include "include/base/cef_string16.h" #include "include/internal/cef_string_types.h" --- cef_binary_3.3359.1774.gd49d25f_windows32/include/base/cef_bind_helpers.h.orig 2018-05-17 11:46:05.000000000 +0200 +++ cef_binary_3.3359.1774.gd49d25f_windows32/include/base/cef_bind_helpers.h 2019-03-09 16:03:17.830725000 +0100 @@ -272,12 +272,12 @@ // MSVC warns when you try to use Base if T has a private destructor, the // common pattern for refcounted types. It does this even though no attempt to // instantiate Base is made. We disable the warning for this definition. -#if defined(OS_WIN) +#if defined(OS_WIN) && defined(COMPILER_MSVC) #pragma warning(push) #pragma warning(disable : 4624) #endif struct Base : public T, public BaseMixin {}; -#if defined(OS_WIN) +#if defined(OS_WIN) && defined(COMPILER_MSVC) #pragma warning(pop) #endif --- cef_binary_3.3359.1774.gd49d25f_windows32/include/base/internal/cef_atomicops_x86_gcc.h.orig 2019-04-02 20:09:10.287478919 +0200 +++ cef_binary_3.3359.1774.gd49d25f_windows32/include/base/internal/cef_atomicops_x86_gcc.h 2019-04-02 20:09:10.287478919 +0200 @@ -0,0 +1,268 @@ +// Copyright (c) 2011 Google Inc. All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are +// met: +// +// * Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above +// copyright notice, this list of conditions and the following disclaimer +// in the documentation and/or other materials provided with the +// distribution. +// * Neither the name of Google Inc. nor the name Chromium Embedded +// Framework nor the names of its contributors may be used to endorse +// or promote products derived from this software without specific prior +// written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +// Do not include this header file directly. Use base/cef_atomicops.h +// instead. + +#ifndef CEF_INCLUDE_BASE_INTERNAL_CEF_ATOMICOPS_X86_GCC_H_ +#define CEF_INCLUDE_BASE_INTERNAL_CEF_ATOMICOPS_X86_GCC_H_ + +// This struct is not part of the public API of this module; clients may not +// use it. +// Features of this x86. Values may not be correct before main() is run, +// but are set conservatively. +struct AtomicOps_x86CPUFeatureStruct { + bool has_amd_lock_mb_bug; // Processor has AMD memory-barrier bug; do lfence + // after acquire compare-and-swap. +}; +extern struct AtomicOps_x86CPUFeatureStruct AtomicOps_Internalx86CPUFeatures; + +#define ATOMICOPS_COMPILER_BARRIER() __asm__ __volatile__("" : : : "memory") + +namespace base { +namespace subtle { + +// 32-bit low-level operations on any platform. + +inline Atomic32 NoBarrier_CompareAndSwap(volatile Atomic32* ptr, + Atomic32 old_value, + Atomic32 new_value) { + Atomic32 prev; + __asm__ __volatile__("lock; cmpxchgl %1,%2" + : "=a"(prev) + : "q"(new_value), "m"(*ptr), "0"(old_value) + : "memory"); + return prev; +} + +inline Atomic32 NoBarrier_AtomicExchange(volatile Atomic32* ptr, + Atomic32 new_value) { + __asm__ __volatile__("xchgl %1,%0" // The lock prefix is implicit for xchg. + : "=r"(new_value) + : "m"(*ptr), "0"(new_value) + : "memory"); + return new_value; // Now it's the previous value. +} + +inline Atomic32 NoBarrier_AtomicIncrement(volatile Atomic32* ptr, + Atomic32 increment) { + Atomic32 temp = increment; + __asm__ __volatile__("lock; xaddl %0,%1" + : "+r"(temp), "+m"(*ptr) + : + : "memory"); + // temp now holds the old value of *ptr + return temp + increment; +} + +inline Atomic32 Barrier_AtomicIncrement(volatile Atomic32* ptr, + Atomic32 increment) { + Atomic32 temp = increment; + __asm__ __volatile__("lock; xaddl %0,%1" + : "+r"(temp), "+m"(*ptr) + : + : "memory"); + // temp now holds the old value of *ptr + if (AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug) { + __asm__ __volatile__("lfence" : : : "memory"); + } + return temp + increment; +} + +inline Atomic32 Acquire_CompareAndSwap(volatile Atomic32* ptr, + Atomic32 old_value, + Atomic32 new_value) { + Atomic32 x = NoBarrier_CompareAndSwap(ptr, old_value, new_value); + if (AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug) { + __asm__ __volatile__("lfence" : : : "memory"); + } + return x; +} + +inline Atomic32 Release_CompareAndSwap(volatile Atomic32* ptr, + Atomic32 old_value, + Atomic32 new_value) { + return NoBarrier_CompareAndSwap(ptr, old_value, new_value); +} + +inline void NoBarrier_Store(volatile Atomic32* ptr, Atomic32 value) { + *ptr = value; +} + +inline void MemoryBarrier() { + __asm__ __volatile__("mfence" : : : "memory"); +} + +inline void Acquire_Store(volatile Atomic32* ptr, Atomic32 value) { + *ptr = value; + MemoryBarrier(); +} + +inline void Release_Store(volatile Atomic32* ptr, Atomic32 value) { + ATOMICOPS_COMPILER_BARRIER(); + *ptr = value; // An x86 store acts as a release barrier. + // See comments in Atomic64 version of Release_Store(), below. +} + +inline Atomic32 NoBarrier_Load(volatile const Atomic32* ptr) { + return *ptr; +} + +inline Atomic32 Acquire_Load(volatile const Atomic32* ptr) { + Atomic32 value = *ptr; // An x86 load acts as a acquire barrier. + // See comments in Atomic64 version of Release_Store(), below. + ATOMICOPS_COMPILER_BARRIER(); + return value; +} + +inline Atomic32 Release_Load(volatile const Atomic32* ptr) { + MemoryBarrier(); + return *ptr; +} + +#if defined(__x86_64__) + +// 64-bit low-level operations on 64-bit platform. + +inline Atomic64 NoBarrier_CompareAndSwap(volatile Atomic64* ptr, + Atomic64 old_value, + Atomic64 new_value) { + Atomic64 prev; + __asm__ __volatile__("lock; cmpxchgq %1,%2" + : "=a"(prev) + : "q"(new_value), "m"(*ptr), "0"(old_value) + : "memory"); + return prev; +} + +inline Atomic64 NoBarrier_AtomicExchange(volatile Atomic64* ptr, + Atomic64 new_value) { + __asm__ __volatile__("xchgq %1,%0" // The lock prefix is implicit for xchg. + : "=r"(new_value) + : "m"(*ptr), "0"(new_value) + : "memory"); + return new_value; // Now it's the previous value. +} + +inline Atomic64 NoBarrier_AtomicIncrement(volatile Atomic64* ptr, + Atomic64 increment) { + Atomic64 temp = increment; + __asm__ __volatile__("lock; xaddq %0,%1" + : "+r"(temp), "+m"(*ptr) + : + : "memory"); + // temp now contains the previous value of *ptr + return temp + increment; +} + +inline Atomic64 Barrier_AtomicIncrement(volatile Atomic64* ptr, + Atomic64 increment) { + Atomic64 temp = increment; + __asm__ __volatile__("lock; xaddq %0,%1" + : "+r"(temp), "+m"(*ptr) + : + : "memory"); + // temp now contains the previous value of *ptr + if (AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug) { + __asm__ __volatile__("lfence" : : : "memory"); + } + return temp + increment; +} + +inline void NoBarrier_Store(volatile Atomic64* ptr, Atomic64 value) { + *ptr = value; +} + +inline void Acquire_Store(volatile Atomic64* ptr, Atomic64 value) { + *ptr = value; + MemoryBarrier(); +} + +inline void Release_Store(volatile Atomic64* ptr, Atomic64 value) { + ATOMICOPS_COMPILER_BARRIER(); + + *ptr = value; // An x86 store acts as a release barrier + // for current AMD/Intel chips as of Jan 2008. + // See also Acquire_Load(), below. + + // When new chips come out, check: + // IA-32 Intel Architecture Software Developer's Manual, Volume 3: + // System Programming Guide, Chatper 7: Multiple-processor management, + // Section 7.2, Memory Ordering. + // Last seen at: + // http://developer.intel.com/design/pentium4/manuals/index_new.htm + // + // x86 stores/loads fail to act as barriers for a few instructions (clflush + // maskmovdqu maskmovq movntdq movnti movntpd movntps movntq) but these are + // not generated by the compiler, and are rare. Users of these instructions + // need to know about cache behaviour in any case since all of these involve + // either flushing cache lines or non-temporal cache hints. +} + +inline Atomic64 NoBarrier_Load(volatile const Atomic64* ptr) { + return *ptr; +} + +inline Atomic64 Acquire_Load(volatile const Atomic64* ptr) { + Atomic64 value = *ptr; // An x86 load acts as a acquire barrier, + // for current AMD/Intel chips as of Jan 2008. + // See also Release_Store(), above. + ATOMICOPS_COMPILER_BARRIER(); + return value; +} + +inline Atomic64 Release_Load(volatile const Atomic64* ptr) { + MemoryBarrier(); + return *ptr; +} + +inline Atomic64 Acquire_CompareAndSwap(volatile Atomic64* ptr, + Atomic64 old_value, + Atomic64 new_value) { + Atomic64 x = NoBarrier_CompareAndSwap(ptr, old_value, new_value); + if (AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug) { + __asm__ __volatile__("lfence" : : : "memory"); + } + return x; +} + +inline Atomic64 Release_CompareAndSwap(volatile Atomic64* ptr, + Atomic64 old_value, + Atomic64 new_value) { + return NoBarrier_CompareAndSwap(ptr, old_value, new_value); +} + +#endif // defined(__x86_64__) + +} // namespace base::subtle +} // namespace base + +#undef ATOMICOPS_COMPILER_BARRIER + +#endif // CEF_INCLUDE_BASE_INTERNAL_CEF_ATOMICOPS_X86_GCC_H_ --- cef_binary_3.3359.1774.gd49d25f_windows32/cmake/cef_variables.cmake.orig 2019-04-02 19:37:47.332457010 +0200 +++ cef_binary_3.3359.1774.gd49d25f_windows32/cmake/cef_variables.cmake 2019-03-09 14:17:10.333854000 +0100 @@ -70,6 +70,8 @@ # Linux configuration. # +set(OS_LINUX true) +set(OS_WINDOWS false) if(OS_LINUX) # Platform-specific compiler/linker flags. set(CEF_LIBTYPE SHARED) @@ -185,21 +187,24 @@ ) # CEF directory paths. + # CEF directory paths. set(CEF_RESOURCE_DIR "${_CEF_ROOT}/Resources") - set(CEF_BINARY_DIR "${_CEF_ROOT}/${CMAKE_BUILD_TYPE}") + set(CEF_BINARY_DIR "${_CEF_ROOT}/$") set(CEF_BINARY_DIR_DEBUG "${_CEF_ROOT}/Debug") set(CEF_BINARY_DIR_RELEASE "${_CEF_ROOT}/Release") # CEF library paths. - set(CEF_LIB_DEBUG "${CEF_BINARY_DIR_DEBUG}/libcef.so") - set(CEF_LIB_RELEASE "${CEF_BINARY_DIR_RELEASE}/libcef.so") + set(CEF_LIB_DEBUG "${CEF_BINARY_DIR_DEBUG}/libcef.lib") + set(CEF_LIB_RELEASE "${CEF_BINARY_DIR_RELEASE}/libcef.lib") # List of CEF binary files. set(CEF_BINARY_FILES - chrome-sandbox - libcef.so - libEGL.so - libGLESv2.so + chrome_elf.dll + d3dcompiler_43.dll + d3dcompiler_47.dll + libcef.dll + libEGL.dll + libGLESv2.dll natives_blob.bin snapshot_blob.bin v8_context_snapshot.bin @@ -216,6 +221,25 @@ icudtl.dat locales ) + + if(USE_SANDBOX) + list(APPEND CEF_COMPILER_DEFINES + PSAPI_VERSION=1 # Required by cef_sandbox.lib + CEF_USE_SANDBOX # Used by apps to test if the sandbox is enabled + ) + + # Libraries required by cef_sandbox.lib. + set(CEF_SANDBOX_STANDARD_LIBS + dbghelp.lib + psapi.lib + version.lib + winmm.lib + ) + + # CEF sandbox library paths. + set(CEF_SANDBOX_LIB_DEBUG "${CEF_BINARY_DIR_DEBUG}/cef_sandbox.lib") + set(CEF_SANDBOX_LIB_RELEASE "${CEF_BINARY_DIR_RELEASE}/cef_sandbox.lib") + endif() endif()